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    * ISA additions and extensions:
          o New instructions LZCNT, POPCNT, EXTRQ/INSERTQ, MOVNTSD/MOVNTSS
          o Extension to the AMD64 instruction set during 2007; it is unclear whether AMD plans this for Revision G or Revision H chips.
          o New SIMD instruction set and new, wide SIMD units; in a yet unspecified time frame.
          o Implementation and possibly adding extensions of SSSE3 (which was called "SSE4" prior to its official name announced) and/or SSE4 , which AMD codenamed SSE4a.

    * Execution Datapath enhancements:
          o More aggressive prefetching (16 bytes to 32 bytes)
          o Out of order loads
          o 128 bit wide Floating point units
          o Larger Out of Order (OoO) buffers
          o Greater number of entries in Branch Target Buffer
          o Probable new additions to micro-ops ROM

    * Integration of new technologies onto CPU die:
          o Four processor cores (Quad-core)
          o independently changeable core voltages
          o Split Power Planes, first dubbed Dynamic Independent Core Engagement or D.I.C.E. by AMD and is now known as Enhanced Cool 'n' Quiet, which "clock-gen" or PLL (Phase-locked loop) present in each core and the northbridge, allowing the cores and the northbridge to scale up and down power consumptions automatically. [11]
          o Large Level-3 non-inclusive cache, initially expected to be a minimum of 2MB shared cache between processing cores on a single die (each with 512 KB of independent second-level cache).
          o Z-RAM technology, projected to bring 4-5 times the cell density of current SRAM for CPU cache, which may or may not be in time for 2007 implementation.

    * Improvements in the Memory Subsystem:
          o 48-bit memory addressing for the address BUS of massive memory subsystems
          o Simultaneous DDR2, DDR3 support
          o FB-DIMM support in server processors for Opterons after year 2008
          o Memory mirroring support and Enhanced RAS
          o Possible use of an intrim socket dubbed "Socket AM2+" which only supports HT 3.0 and DDR2.
          o Possible use of new socket (Socket AM3), containing both DDR2 and DDR3 controllers: AM3 chips to be backward compatible with Socket AM2 motherboards; but socket AM2 chips will not be compatible with AM3 motherboards. Recent information indicates that Socket AM3 may not be deployed until AMD's 45nm manufacturing process is ready, due to the anticipated slow adoption of DDR3 (despite both bandwidth and energy efficiency over DDR2); [12].
          o In recent reports[13], AMD K8L CPUs will adapt two sockets namely "Socket AM2+" and "Socket F+", which is capable of running HyperTransport 3.0 with the use of DDR2 DIMMs. The "Socket AM3" will be postsponed until 2008, the two suggested sockets have the same pin definitions as the old Socket AM2 and Socket F with the only difference of the capability of running HyperTransport 3.0 at working frequencies higher than 1.6 GHz.
          o Quad-core revision will have two independent memory controllers (two 64-bit) each with its own physical address space thus giving an opportunity to better utilize the available bandwidth in case of random memory accesses, mostly beneficial in multi-threaded environment. This approach is in a contrary to the previous "interleaved" design, where the two 64-bit channels are bounded to a single [common] address space, and it will be the first single-chip implementation of NUMA memory access.

    * Improvements in System Interconnect:
          o HyperTransport retry support
          o Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.
          o Support for HyperTransport 4.0 at an unspecified date; according to techreport.com[14] and some other sources.
          o Increased number of HyperTransport links per processor package to 4 (from 3 in current Opterons), and maximum socket count to 32; this will be implemented in Revision H Opterons.

    * Platform Level Enhancements with additional functionalities:
          o Official support for coprocessors connected via HyperTransport Expansion Slot (HTX)
          o Opening cache coherent HyperTransport (ccHT) standard to third party developments: Torrenza initiative.
          o Vector coprocessor support, which will bring 1-2 orders of FP/SIMD performance increase if a specialized processor is attached via coherent HyperTransport link in a specialized socket.
          o Possible integration of GPU functionalities onto a CPU die or package.